In the design step of a semiconductor integrated circuit, a logic circuit diagram is designed, based on a specification data on a circuit, and a layout data is created, based on the logic circuit diagram. Whether or not the created layout data is correctly designed in accordance with a design rule originally intended by a designer is verified (hereinafter referred to as “layout check”).
The layout check is performed by using Electronic Design Automation (EDA) tools such as Design Rule Checking (DRC) that verifies whether or not the layout violates a geometrical design rule determined from the restriction of manufacturing equipment, Layout Versus Schematic (LVS) that verifies whether or not a data on devices and connections between the devices prepared in a logic circuit schematic design step is correctly realized in the layout data, and Electric Rule Check (ERC) that verifies the electrical connection of a logic circuit diagram. The layout data is completed at a time when any error is not detected in a verification performed by the DRC, LVS or the like (Japanese Patent Application Laid-Open No. 1991-171648).